Design of a Low Power 10T SRAM Cell
نویسندگان
چکیده
SRAM is a semiconductor memory cell. In this paper, a 10T SRAM cell is designed by using cadence virtuoso tool in 180nm CMOS technology. Its performance characteristics such as power, delay, and power delay product are analysed. 10T SRAM cell is basically 6T SRAM cell with 4 extra transistors. In this 10T SRAM cell, additional read circuitry is attached to avoid flipping of cell. The power dissipation, delay, and power delay product of the designed 10T SRAM cell in 180nm CMOS technology are found to be 22.08 x 10 -9 W, 39.95 x 10 -9 s and 0.8820 x 10 -15 Ws respectively.
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